View AM29LV6402MH110RPHI_670670.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Am29LV6402M
Data Sheet
RETIRED PRODUCT
This product has been retired and is not available for designs. For new and current designs, S29GL128N supersedes Am29LV6402M and is the factory-recommended migration path. Please refer to the S29GL128N Data Sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 27552
Revision B
Amendment +1
Issue Date January 23, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV6402M
128 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/OTM Control
This product has been retired and is not available for designs. For new and current designs, S29GL128N supersedes Am29LV6402M and is the factory-recommended migration path. Please refer to the S29GL128N Data Sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Single power supply operation -- 3 volt read, erase, and program operations VersatileI/O control -- Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V
TM
-- 4-doubleword/8-word page read buffer -- 16-doubleword/32-word write buffer Low power consumption (typical values at 3.0 V, 5 MHz) -- 26 mA typical active read current -- 100 mA typical erase/program current -- 2 A typical standby mode current Package options -- 80-ball Fortified BGA SOFTWARE & HARDWARE FEATURES Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word or byte programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Sector Group Protection: hardware-level method of preventing write operations within a sector group -- Temporary Sector Unprotect: VID-level method of changing code in locked sectors -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device -- Ready/Busy# output (RY/BY#) detects program or erase cycle completion
Manufactured on 0.23 m MirrorBit process technology
TM
SecSiTM (Secured Silicon) Sector region -- 128-doubleword/256-word sector for permanent, secure identification through an 8-doubleword/16-word random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked at the factory or by the customer Flexible sector architecture -- One hundred twenty-eight 32 Kdoubleword (64 Kword) sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection 100,000 erase cycles per sector 20-year data retention at 125C PERFORMANCE CHARACTERISTICS High performance -- 100 ns access time -- 30 ns page read times -- 0.5 s typical sector erase time -- 22 s typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates
Publication# 27552 Rev: B Amendment/1 Issue Date: January 23, 2006
Refer to AMD's Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29LV6402M consists of two 64 Mbit, 3.0 volt single power supply flash memory devices and is organized as 4,194,304 doublewords or 8,388,608 words. The device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the WORD# input. The device can be programmed either in the host system or in standard EPROM programmers. An access time of 100 or 110 ns is available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and the Ordering Information sections. The device is offered in an 80-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) outputs to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSiTM (Secured Silicon) Sector provides a 128-doubleword/256-word area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. AMD MirrorBitTM flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit products, including migration information, data sheets, application notes, and software drivers, please see www.amd.comFlash MemoryProduct InformationMirrorBitFlash InformationTechnical Documentation. The following is a partial list of documents closely related to this product: MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs
2
Am29LV6402M
January 23, 2006
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Memory Block diagram . . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6 Special Package Handling Instructions .................................... 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 x16 Mode .................................................................................. 7 x32 Mode .................................................................................. 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations ....................................................... 9
Chip Erase Command Sequence ........................................... 29 Sector Erase Command Sequence ........................................ 29 Erase Suspend/Erase Resume Commands ........................... 29
Figure 7. Erase Operation .............................................................. 30 Table 10. Command Definitions (x32 Mode, WORD# = VIH) ......... 31 Table 11. Command Definitions (x16 Mode, WORD# = VIL).......... 32
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 33 DQ7 and DQ5: Data# Polling .................................................. 33
Figure 8. Data# Polling Algorithm .................................................. 33
DQ6 and DQ14: Toggle Bits I ................................................. 34
Figure 9. Toggle Bit Algorithm ........................................................ 35
VersatileIOTM (VIO) Control ........................................................ 9 Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................10
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10 Accelerated Program Operation ......................................................10 Autoselect Functions .......................................................................10
DQ2 and DQ10: Toggle Bits II ................................................ 35 Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10 ............ 35 DQ5 and DQ13: Exceeded Timing Limits ............................... 36 DQ3 and DQ11: Sector Erase Timer ...................................... 36 DQ1: Write-to-Buffer Abort ..................................................... 37
Table 12. Write Operation Status................................................... 37
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 38
Figure 10. Maximum Negative Overshoot Waveform ................... 38 Figure 11. Maximum Positive Overshoot Waveform ..................... 38
Automatic Sleep Mode ........................................................... 11 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12 Table 3. Autoselect Codes, (High Voltage Method) ....................... 15
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 12. Test Setup ..................................................................... 40 Table 13. Test Specifications ......................................................... 40
Sector Group Protection and Unprotection ............................. 16
Table 4. Sector Group Protection/Unprotection Address Table ..... 16
Key to Switching Waveforms. . . . . . . . . . . . . . . . 40
Figure 13. Input Waveforms and Measurement Levels ...................................................................... 40
Temporary Sector Group Unprotect ....................................... 17
Figure 1. Temporary Sector Group Unprotect Operation ................17 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...18
SecSi (Secured Silicon) Sector Flash Memory Region .......... 19
Table 5. SecSi Sector Contents ...................................................... 19 Figure 3. SecSi Sector Protect Verify ..............................................20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 Read-Only Operations ........................................................... 41
Figure 14. Read Operation Timings ............................................... 41 Figure 15. Page Read Timings ...................................................... 42
Hardware Data Protection ...................................................... 20
Low VCC Write Inhibit .....................................................................20 Write Pulse "Glitch" Protection ........................................................20 Logical Inhibit ..................................................................................20 Power-Up Write Inhibit ....................................................................20
Hardware Reset (RESET#) .................................................... 43
Figure 16. Reset Timings ............................................................... 43
Erase and Program Operations .............................................. 44
Figure 17. Program Operation Timings .......................................... 45 Figure 18. Accelerated Program Timing Diagram .......................... 45 Figure 19. Chip/Sector Erase Operation Timings .......................... 46 Figure 20. Data# Polling Timings (During Embedded Algorithms) . 47 Figure 21. Toggle Bit Timings (During Embedded Algorithms) ...... 48 Figure 22. DQ2 vs. DQ6 ................................................................. 48
Common Flash Memory Interface (CFI) . . . . . . . 20
Table 6. CFI Query Identification String ..........................................21 Table 7. System Interface String..................................................... 21 Table 8. Device Geometry Definition ..............................................22 Table 9. Primary Vendor-Specific Extended Query ........................23
Temporary Sector Unprotect .................................................. 49
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 49 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 50
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ................................................................ 24 Reset Command ..................................................................... 24 Autoselect Command Sequence ............................................ 24 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25 Doubleword/Word Program Command Sequence ................. 25
Unlock Bypass Command Sequence ..............................................25 Write Buffer Programming ...............................................................25 Accelerated Program ......................................................................26 Figure 4. Write Buffer Programming Operation ...............................27 Figure 5. Program Operation ..........................................................28
Alternate CE# Controlled Erase and Program Operations ..... 51
Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings .......................................................................... 52
Program Suspend/Program Resume Command Sequence ... 28
Figure 6. Program Suspend/Program Resume ...............................28
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 52 Erase And Programming Performance. . . . . . . . 53 TSOP Pin and BGA Package Capacitance . . . . . 53 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LSB080--80-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11 mm Package .............................................................. 54 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
January 23, 2006
Am29LV6402M
3
PRODUCT SELECTOR GUIDE
Part Number Speed Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (tPACC) Max. OE# Access Time (ns) VCC = 3.0-3.6 V Am29LV1282M 100R (VIO = 2.7-3.6 V) 100 100 30 30 110R (VIO = 1.65-3.6 V) 110 110 30 30
MCP BLOCK DIAGRAM
A21 to A0 RY/BY# CE# OE# WE# RESET# WORD# WP#/ACC 64 Mbit Flash Memory #1
DQ23/A-1 to DQ16; DQ7-DQ0 X16
X32
DQ31 to DQ0
64 Mbit Flash Memory #2
X16 DQ31/A-1 to DQ24; DQ15 TO DQ8
Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board.
4
Am29LV6402M
January 23, 2006
FLASH MEMORY BLOCK DIAGRAM
RY/BY# VCC VSS Erase Voltage Generator VIO Input/Output Buffers Sector Switches DQ31-DQ0 (A-1)
RESET# WE# WP#/ACC WORD#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A21-A0
Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board.
January 23, 2006
Am29LV6402M
5
CONNECTION DIAGRAMS
80-ball Fortified BGA Top View, Balls Facing Down
A8 DQ21 A7 DQ23/A-1 A6 DQ30 A5 VSS A4 VCC A3 DQ31/A-1 A2 DQ18 A1 RFU
B8 DQ28 B7 A13 B6 A9 B5 WE# B4
C8 RFU C7 A12 C6 A8 C5 RESET# C4
D8 RFU D7 A14 D6 A10 D5 A21 D4 A18 D3 A6 D2 A2 D1 RFU
E8 VIO E7 A15 E6 A11 E5 A19 E4 A20 E3 A5 E2 A1 E1 RFU
F8 VSS F7 A16 F6 DQ7 F5 DQ5 F4 DQ2 F3 DQ0 F2 A0 F1 RFU
G8 RFU G7 WORD# G6 DQ14 G5 DQ12 G4 DQ10 G3 DQ8 G2 CE# G1 VIO
H8 RFU H7 DQ15 H6 DQ13 H5 VCC H4 DQ11 H3 DQ9 H2 OE# H1 RFU
J8 DQ29 J7 VSS J6 DQ6 J5 DQ4 J4 DQ3 J3 DQ1 J2 VSS J1 DQ24
K8 DQ22 K7 DQ20 K6 DQ27 K5 DQ26 K4 DQ19 K3 DQ17 K2 VCC K1 DQ25
RY/BY# WP#/ACC B3 A7 B2 A3 B1 DQ16 C3 A17 C2 A4 C1 VCC
Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not yet been determined. Contact AMD for further information.
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP, SSOP). The package and/or data integrity may be
compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
6
Am29LV6402M
January 23, 2006
PIN CONFIGURATION
A-1
= Least significant address bit for the 16-bit data bus, and selects between the high and low word. A -1 is not used for the 32-bit mode (WORD# = VIH). = 22-bit address bus for 128 Mb device. = 32-bit data inputs/outputs/float = Selects 16-bit or 32-bit mode. When WORD# = VIH, data is output on DQ31-DQ0. When WORD# = VIL, data is output on DQ15-DQ0. = Chip Enable Input. = Output Enable Input. = Write enable. VSS RY/BY# = Device ground = Ready/Busy output and open drain. When RY/BY# = VOH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation.
A21-A0 DQ31-DQ0 WORD#
WP#/ACC VCC RESET# NC
= Write Protect input/Acceleration input. = Power Supply (2.7 V to 3.6 V) = Hardware reset input = Pin not connected internally
CE# OE# WE#
LOGIC SYMBOLS x16 Mode
23 A21 to A-1 CE# OE# WE# WP#/ACC RESET# WP# WORD# VIO RY/BY# DQ15-DQ0 CE# OE# WE# WP#/ACC RESET# WP# WORD# VIO RY/BY# 16
x32 Mode
22 A21-A0 DQ31-DQ0 32
Note:In x16 mode, DQ31 and DQ23 must be connected to each other on the board.
January 23, 2006
Am29LV6402M
7
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
Am29LV6402M
H
100R
PH
I
TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE TYPE PH = 80-Ball Fortified Ball Grid Array (FBGA), 1.00 mm ball pitch, 13 x 11 mm, (LSB080) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = VIL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected
DEVICE NUMBER/DESCRIPTION Am29LV6402MH/L 2 x 64 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBitTM Uniform Sector Flash Memory 3.0 Volt-only Read, Program, and Erase
Valid Combinations Valid Combinations for Fortified BGA Package Order Number Package Marking Speed VCC VIO (ns) Range Range 2.7- 3.6 V 1.65- 3.6 V Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am29LV6402MH100R, PHI L6402MH10R I Am29LV6402ML100R Am29LV6402MH110R, PHI L6402ML11R Am29LV6402ML110R
I
100 110
3.0- 3.6 V
8
Am29LV6402M
January 23, 2006
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Device Bus Operations
DQ31-DQ16
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Sector Group Protect (Note 2) Sector Group Unprotect (Note 2) Temporary Sector Group Unprotect
CE# L L L VCC 0.3 V L X L
OE# L H H X H X H
WE# H L L X H X L
RESET# H H H VCC 0.3 V H L VID
WP#
ACC
Addresses (Note 2) AIN AIN AIN X X X SA, A6 =L, A3=L, A2=L, A1=H, A0=L SA, A6=H, A3=L, A2=L, A1=H, A0=L AIN
DQ15- DQ0 DOUT
WORD# = VIH DOUT
WORD# = VIL
X (Note 3) (Note 3) X X X H
X X VHH H X X X
DQ31-DQ16 = High-Z, (Note 4) (Note 4) DQ31 & (Note 4) (Note 4) DQ23= A-1 High-Z High-Z High-Z (Note 4) High-Z High-Z High-Z X High-Z High-Z High-Z X
L
H
L
VID
H
X
(Note 4)
X
X
X
X
X
VID
H
X
(Note 4) (Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 11.5-12.5V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0 in doubleword mode; A21:A-1 in word mode. Sector addresses are A21:A15 in both modes. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Unprotection" section. 3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in "Sector Group Protection and Unprotection". All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The WORD# pin controls whether the device data I/O pins operate in the word or doubleword configuration. If the WORD# pin is set at VIH, the device is in doubleword configuration, DQ31-DQ0 are active and controlled by CE# and OE#. If the WORD# pin is set at VIL, the device is in word configuration, and only data I/O pins DQ15-DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ31-DQ16 are tri-stated, and the DQ23 and
DQ31 pins are used as inputs for the LSB (A-1) address function.
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See Ordering Information for VIO options on this device.
January 23, 2006
Am29LV6402M
9
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 doublewords/8 words. The appropriate page is selected by the higher address bits A(max)-A2. Address bits A1-A0 in doubleword mode (A1-A-1 in word mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.
using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system write to a maximum of 16 doublewords/32 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Doubleword/Word Program Command Sequence" section has details on programming data to the device
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than
10
Am29LV6402M
January 23, 2006
VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification.
SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RE-
January 23, 2006
Am29LV6402M
11
Table 2.
A21-A15 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Sector Address Table
Sector Size (Kwords/Kdoublewords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 0200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 32-bit Address Range (in hexadecimal) 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF
12
Am29LV6402M
January 23, 2006
Table 2.
A21-A15 Sector SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF 400000-40FFFF 410000-41FFFF 420000-42FFFF 430000-43FFFF 440000-44FFFF 450000-45FFFF 460000-46FFFF 470000-47FFFF 480000-48FFFF 490000-49FFFF 4A0000-4AFFFF 4B0000-4BFFFF 4C0000-4CFFFF 4D0000-4DFFFF 4E0000-4EFFFF 4F0000-4FFFFF 500000-50FFFF 510000-51FFFF 520000-52FFFF 530000-53FFFF 540000-54FFFF 550000-55FFFF 560000-56FFFF 570000-57FFFF 580000-58FFFF 590000-59FFFF 5A0000-5AFFFF 5B0000-5BFFFF 5C0000-5CFFFF 5D0000-5DFFFF 5E0000-5EFFFF 32-bit Address Range (in hexadecimal) 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF 200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF 268000-26FFFF 270000-277FFF 278000-27FFFF 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF
January 23, 2006
Am29LV6402M
13
Table 2.
A21-A15 Sector SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Sector Address Table (Continued)
Sector Size (Kwords/Kdoublewords) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16-bit Address Range (in hexadecimal) 5F0000-5FFFFF 600000-60FFFF 610000-61FFFF 620000-62FFFF 630000-63FFFF 640000-64FFFF 650000-65FFFF 660000-66FFFF 670000-67FFFF 680000-68FFFF 690000-69FFFF 6A0000-6AFFFF 6B0000-6BFFFF 6C0000-6CFFFF 6D0000-6DFFFF 6E0000-6EFFFF 6F0000-6FFFFF 700000-70FFFF 710000-71FFFF 720000-72FFFF 730000-73FFFF 740000-74FFFF 750000-75FFFF 760000-76FFFF 770000-77FFFF 780000-78FFFF 790000-79FFFF 7A0000-7AFFFF 7B0000-7BFFFF 7C0000-7CFFFF 7D0000-7DFFFF 7E0000-7EFFFF 7F0000-7FFFFF 32-bit Address Range (in hexadecimal) 2F8000-2FFFFF 300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF
14
Am29LV6402M
January 23, 2006
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 3.
In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tables 10 and 11. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.
Table 3.
Description CE# OE# WE#
Autoselect Codes, (High Voltage Method)
A9 A8 to A7 X A6 A5 to A4 X A3 to A2 L L
A21 A14 to to A15 A10 X X
DQ23 to DQ16
A1 A0
WORD# WORD# = VIH = VIL
00 22 22 22 X X X X X X
DQ7 to DQ0
Manufacturer ID: AMD Device ID Cycle 1 Cycle 2 Cycle 3
L
L
H
VID
L
L L H H H
L H L H L
01h 7Eh 0Ch 01h 01h (protected), 00h (unprotected) 98h (factory locked), 18h (not factory locked)
L
L
H
X
X
VID
X
L
X
H H
Sector Protection Verification SecSi Sector Indicator Bit (DQ7), WP# protects highest address sector SecSi Sector Indicator Bit (DQ7), WP# protects lowest address sector
L
L
H
SA
X
VID
X
L
X
L
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
L
L
H
X
X
VID
X
L
X
L
H
H
X
X
88h (factory locked), 08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
January 23, 2006
Am29LV6402M
15
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Autoselect Mode section for details.
Table 4.
Sector Group Protection/Unprotection Address Table
A21-A15 0000000 0000001 0000010 0000011 00001xx 00010xx 00011xx 00100xx 00101xx 00110xx 00111xx 01000xx 01001xx 01010xx 01011xx 01100xx 01101xx 01110xx 01111xx 10000xx 10001xx 10010xx 10011xx 10100xx 10101xx 10110xx 10111xx 11000xx 11001xx 11010xx 11011xx 11100xx 11101xx 11110xx 1111100 1111101 1111110 1111111 SA0 SA1 SA2 SA3
Sector Group
SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 SA64-SA67 SA68-SA71 SA72-SA75 SA76-SA79 SA80-SA83 SA84-SA87 SA88-SA91 SA92-SA95 SA96-SA99 SA100-SA103 SA104-SA107 SA108-SA111 SA112-SA115 SA116-SA119 SA120-SA123 SA124 SA125 SA126 SA127
16
Am29LV6402M
January 23, 2006
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in "DC Characteristics". If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Group Unprotect
Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Figure 5). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature.
Temporary Sector Group Unprotect Completed (Note 2)
Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
January 23, 2006
Am29LV6402M
17
START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Group Unprotect Mode
No
First Write Cycle = 60h?
First Write Cycle = 60h?
No
Temporary Sector Group Unprotect Mode
Yes Set up sector group address No
Yes All sector groups protected? Yes Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6 = 1, A1 = 1, A0 = 0 Reset PLSCNT = 1 Wait 15 ms
Sector Group Protect: Write 60h to sector group address with A6 = 0, A1 = 1, A0 = 0
Wait 150 s
Increment PLSCNT
Verify Sector Group Protect: Write 40h to sector group address twith A6 = 0, A1 = 1, A0 = 0
Read from sector group address with A6 = 0, A1 = 1, A0 = 0 No No PLSCNT = 25? Data = 01h?
Increment PLSCNT
Verify Sector Group Unprotect: Write 40h to sector group address with A6 = 1, A1 = 1, A0 = 0
Yes Yes Protect another sector group? No Remove VID from RESET# Yes
Read from sector group address with A6 = 1, A1 = 1, A0 = 0 No Set up next sector group address Data = 00h?
No
PLSCNT = 1000? Yes
Device failed
Yes
Device failed Write reset command
Last sector group verified? Yes Remove VID from RESET#
No
Sector Group Protect Algorithm
Sector Group Protect complete
Sector Group Unprotect Algorithm
Write reset command
Sector Group Unprotect complete
Figure 2.
In-System Sector Group Protect/Unprotect Algorithms
18
Am29LV6402M
January 23, 2006
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 doublewords/256 words in length, and uses SecSi Sector Indicator Bits (DQ7 and DQ15) to indicate whether or not the SecSi Sector is locked when shipped from the factory. These bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factor y locke d or custom er lockable. The factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bits permanently set to a "1." The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bits prevent customer-lockable devices from being used to replace devices that are factory locked. The SecSi sector address space in this device is allocated as follows: Table 5.
SecSi Sector Address Range x32 000000h- 000007h 000008h- 00007Fh x16 000000h- 00000Fh 000010h- 0000FFh
Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. A factory locked device has an 8-doubleword/16-word random ESN at addresses 000000h-000007h. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The devices are then shipped from AMD's factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD's ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-doubleword/256 word SecSi sector. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See To reduce power consumption read Lower Byte only.. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array.
SecSi Sector Contents
Standard Factory Locked ESN Unavailable ExpressFlash Factory Locked ESN or determined by customer Determined by customer Customer Lockable
Determined by customer
The system accesses the SecSi Sector through a command sequence (see "Enter SecSi Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0.
January 23, 2006
Am29LV6402M
19
START RESET# = VIH or VID IH ID Wait 1 ms Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID IH ID from RESET# Write reset command SecSi Sector Protect Verify complete
caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Figure 3.
SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 10 and 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6-9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6-9. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.
20
Am29LV6402M
January 23, 2006
Table 6.
Addresses (x32) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 00005151h 00005252h 00005959h 00000202h 00000000h 00004040h 00000000h 00000000h 00000000h 00000000h 00000000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 7.
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 00002727h 00003636h 00000000h 00000000h 00000707h 00000707h 00000A0Ah 00000000h 00000101h 00000505h 00000404h 00000000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
January 23, 2006
Am29LV6402M
21
Table 8.
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 00001717h 00000101h 00000000h 00000505h 00000000h 00000101h 00007F7Fh 00000000h 00000000h 00000101h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h
Device Geometry Definition
Description
Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
N
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
22
Am29LV6402M
January 23, 2006
Table 9.
Addresses (x16) 40h 41h 42h 43h 44h 45h Data 00005050h 00005252h 00004949h 00003131h 00003333h 000000808h
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0010b = 0.23 m MirrorBit
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
000000202h 00000101h 00000101h 00000404h 00000000h 00000000h 00000101h 0000B5B5h
Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag
4Eh
0000C5C5h
4Fh
00000404h/ 00000505h
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported
50h
00000101h
Note:To reduce power consumption read Lower Byte only.
January 23, 2006
Am29LV6402M
23
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 or DQ13 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 or DQ9 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 or DQ13 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 11 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: A read cycle at address XX00h returns the manufacturer code. Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in doubleword mode returns 0101h if the sector is protected, or 0000h if it is unprotected. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
24
Am29LV6402M
January 23, 2006
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-doubleword/16-word random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also "SecSi (Secured Silicon) Sector Flash Memory Region" for further information.
dard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 2020h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 9090h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 doublewords/32 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 0505h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A23-A4. All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts
Doubleword/Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 and DQ15 or DQ6 and DQ14. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 and/or DQ13 = 1, or cause the DQ7 and/or DQ15, and DQ6 and/or DQ14 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the stan-
January 23, 2006
Am29LV6402M
25
to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host s y s t e m mu s t t h e r e fo r e a c c o u n t fo r l o a d i n g a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7 and DQ15, DQ6 and DQ14, DQ5 and DQ13, and DQ1 and DQ9 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 and DQ9 = 1, DQ7 and DQ15 = DATA# (for the last address location loaded), DQ6 and DQ14 = toggle, and DQ5 and DQ13 =0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 and/or DQ13= 1, or cause the DQ7 and/or DQ15 and DQ6 and/or DQ14 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.
26
Am29LV6402M
January 23, 2006
Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1(WC) and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to flash sector address
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page.
Read DQ7 - DQ0 at Last Loaded Address
2.
DQ7 and DQ15 may change simultaneously with DQ5 and DQ13. Therefore, DQ7 and DQ15 should be verified. If this flowchart location was reached because DQ5 and DQ13 = "1", then the device FAILED. If this flowchart location was reached because DQ1= "1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1 and DQ9 =1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5 and DQ13 =1, write the Reset command.
See Tables 10 and 11 for command sequences required for write buffer programming.
3.
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ7 - DQ0 with address = Last Loaded Address No
Yes
4.
(Note 2)
DQ7 = Data? No
Yes
(Note 3)
FAIL or ABORT
PASS
Figure 4.
Write Buffer Programming Operation
January 23, 2006
Am29LV6402M
27
user must use the proper command sequences to enter and exit this region.
START
Write Program Command Sequence
The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 and DQ15 or DQ6 and DQ14 status bits, just as in the standard program operation. See Write Operation Status for more information.
No
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
Yes No
Increment Address
Last Address?
The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.
Yes Programming Completed
Program Operation or Write-to-Buffer Sequence in Progress
Note: See Tables 10 and 11 for program command sequence.
Write address/data XXXh/B0h
Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations
Figure 5.
Program Operation
Wait 15 s
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 s max (5 s typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-time Program area), then
Read data as required
Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors
No
Done reading? Yes Write address/data XXXh/30h Write Program Resume Command Sequence
Device reverts to operation prior to Program Suspend
Figure 6.
Program Suspend/Program Resume
28
Am29LV6402M
January 23, 2006
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 10 and 11 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 and DQ15, DQ6 and DQ14, or DQ2 and DQ10. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 and DQ11 to determine if the sector erase timer has timed out (See the section on DQ3 and DQ11: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can determine the status of the erase operation by reading DQ7 and DQ15, DQ6 and DQ14, or DQ2 and DQ10 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 11 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s (maximum of 20 s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.
January 23, 2006
Am29LV6402M
29
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ15-DQ0. The system can use DQ7 and DQ15, or DQ6 and DQ14 and DQ2 and DQ10 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 and DQ15 or DQ6 and DQ14 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Tables 10 and 11 for program command sequence. 2. See the section on DQ3 and DQ10 for information on the sector erase timer.
Figure 7.
Erase Operation
30
Am29LV6402M
January 23, 2006
Command Definitions
Table 10.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSiTM Sector Factory Protect (Note 10) Sector Protect Verify (Note 12) Cycles
Command Definitions (x32 Mode, WORD# = VIH)
Bus Cycles (Notes 2-5) First Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Addr RA XXX 555 555 555 555 555 555 555 555 SA 555 555 XXX XXX 555 555 XXX XXX 55
Data RD F0F0 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 2929 AAAA AAAA A0A0 9090 AAAA AAAA B0B0 3030 9898
1 1 4 6 4 4 3 4 4 3 1 3 3 2 2 6 6 1 1 1
2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA
5555 5555 5555 5555 5555 5555 5555 5555 5555 5555 PD 0000 5555 5555
555 555 555 555 555 555 555 SA 555 555
9090 9090 9090
X00 X01 X03
00000101 2222 7E7E (Note 10) 0000/ 0101 0000 PD DWC PA PD WBL PD X0E 2222 0C0C X0F 2222 0101
9090 (SA)X02 8888 9090 A0A0 2525 F0F0 2020 XXX PA SA
Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Unlock Bypass Unlock Bypass Program (Note 14) Unlock Bypass Reset (Note 15) Chip Erase Sector Erase Program/Erase Suspend (Note 16) Program/Erase Resume (Note 17) CFI Query (Note 18)
555 555
8080 8080
555 555
AAAA AAAA
2AA 2AA
5555 5555
555 SA
1010 3030
Legend: X = Don't care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. 4. 5. 6. 7. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ31-DQ16 are don't care in command sequences, except for RD, PD, and DWC. Unless otherwise noted, address bits A21-A11 are don't cares. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 and/or DQ13 goes high while the device is providing status information. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ31-DQ16 are don't care. See the Autoselect Command Sequence section for more information. The device ID must be read in three cycles.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. DWC = Doubleword Count. Number of write buffer locations to load minus 1.
11. The total number of cycles in the command sequence is determined by the number of doublewords written to the write buffer. The maximum number of cycles in the command sequence is 21. 12. The data is 0000h for an unprotected sector and 0101h for a protected sector. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
8.
9.
10. If WP# protects the highest address sector, the data is 9898h for factory locked and 1818h for not factory locked. If WP# protects the lowest address sector, the data is 8888h for factory locked and 0808h for not factor locked.
January 23, 2006
Am29LV6402M
31
Table 11.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSiTM Sector Factory Protect (Note 10) Sector Protect Verify (Note 12) Cycles
Command Definitions (x16 Mode, WORD# = VIL)
Bus Cycles (Notes 2-5) First Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Addr RA XXX AAA AAA AAA AAA AAA AAA AAA AAA SA AAA AAA XXX XXX AAA AAA XXX XXX AA
Data RD F0F0 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 2929 AAAA AAAA A0A0 9090 AAAA AAAA B0B0 3030 9898
1 1 4 6 4 4 3 4 4 3 1 3 3 2 2 6 6 1 1 1
555 555 555 555 555 555 555 555 555 555 PA XXX 555 555
5555 5555 5555 5555 5555 5555 5555 5555 5555 5555 PD 0000 5555 5555
AAA AAA AAA AAA AAA AAA AAA SA AAA AAA
9090 9090 9090
X00 X02 X06
0101 7E7E (Note 10) 0000/ 0101 0000 PD WC PA PD WBL PD X1C 0C0C X1E 0101
9090 (SA)X04 8888 9090 A0A0 2525 F0F0 2020 XXX PA SA
Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Unlock Bypass Unlock Bypass Program (Note 14) Unlock Bypass Reset (Note 15) Chip Erase Sector Erase Program/Erase Suspend (Note 16) Program/Erase Resume (Note 17) CFI Query (Note 18)
AAA AAA
8080 8080
AAA AAA
AAAA AAAA
555 555
5555 5555
AAA SA
1010 3030
Legend: X = Don't care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. 4. 5. 6. 7. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ31-DQ15 are don't care in command sequences. Unless otherwise noted, address bits A21-A11 are don't cares. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 and/or DQ13goes high while the device is providing status information. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ31-DQ16 are don't care. See the Autoselect Command Sequence section for more information. The device ID must be read in three cycles.
SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.
11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 12. The data is 0000h for an unprotected sector group and 0101h for a protected sector group. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
8.
9.
10. If WP# protects the highest address sector, the data is 9898h for factory locked and 1818h for not factory locked. If WP# protects the lowest address sector, the data is 8888h for factory locked and 0808h for not factor locked.
32
Am29LV6402M
January 23, 2006
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2 and DQ10, DQ3 and DQ11, DQ5 and DQ13, DQ6 and DQ14, and DQ7 and DQ15. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ15 and DQ6 and DQ14 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 and DQ14-DQ8 may be still invalid. Valid data on DQ15-DQ0 will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7 and DQ15. Figure 8 shows the Data# Polling algorithm. Figure 20 in the AC Characteristics section shows the Data# Polling timing diagram.
DQ7 and DQ5: Data# Polling
The Data# Polling bit, DQ7 and DQ15, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and DQ15 the complement of the datum programmed to DQ7 and DQ15. This DQ7 and DQ15 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7 and DQ15. The system must provide the program address to read valid status information on DQ7 and DQ15. If a program address falls within a protected sector, Data# Polling on DQ7 and DQ15 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7 and DQ15. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7 and DQ15. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7 and DQ15. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 and DQ15 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 and DQ15 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 and DQ15 may change asynchronously with DQ6-DQ0 and DQ14-DQ8 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7 and DQ15. Depending on when the system samples the DQ7 and DQ15 output, it may read the status or valid data. Even if the device has com-
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 and DQ15 should be rechecked even if DQ5 and/or DQ13 = "1" because DQ7 and DQ15 may change simultaneously with DQ5 and DQ13.
Figure 8.
Data# Polling Algorithm
January 23, 2006
Am29LV6402M
33
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 and DQ14 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ14 and DQ2 and DQ10 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 and DQ14 toggle. When the device enters the Erase Suspend mode, DQ6 and DQ14 stop toggling. However, the system must also use DQ2 and DQ10 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 and DQ15 (see the subsection on DQ7 and DQ15: Data# Polling). If a program address falls within a protected sector, DQ6 and DQ14 toggle for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 and DQ14 also toggle during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6 and DQ14. Figure 9 shows the toggle bit algorithm. Figure 21 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ10 and DQ6 and DQ14 in graphical form. See also the subsection on DQ2 and DQ10: Toggle Bits II.
DQ6 and DQ14: Toggle Bits I
Toggle Bit I on DQ6 and DQ14 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 and DQ14 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 and DQ14 stops toggling.
34
Am29LV6402M
January 23, 2006
DQ2 and DQ10: Toggle Bits II
START
Read DQ7-DQ0
The "Toggle Bits II" on DQ2 and DQ10, when used with DQ6 and DQ14, indicate whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bits II are valid after the rising edge of the final WE# pulse in the command sequence. DQ2 and DQ10 toggle when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 and DQ10 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6 and DQ14, by comparison, indicate whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ10 and DQ6 and DQ14. Figure 9 shows the toggle bit algorithm in flowchart form, and the section "DQ2 and DQ10: Toggle Bits II" explains the algor ithm. See also the RY/BY#: Ready/Busy# subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ10 and DQ6 and DQ14 in graphical form.
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle?
No
Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10
Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bits status, it must read DQ15-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bits are not toggling, the device has completed the program or erase operation. The system can read array data on DQ15-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that one of the toggle bits are still toggling, the system also should note whether the value of DQ5 and DQ13 is high (see the section on DQ5 and DQ13). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 and/or DQ13 went high. If the toggle bits are no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 and DQ13= "1" because the toggle bit may stop toggling as DQ5 and DQ13 changes to "1." See the subsections on DQ6 and DQ14 and DQ2 and DQ10 for more information.
Figure 9.
Toggle Bit Algorithm
January 23, 2006
Am29LV6402M
35
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 and/or DQ13 has not gone high. The system may continue to monitor the toggle bits and DQ5 and DQ13 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9).
DQ3 and DQ11: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 and DQ11 to deter mine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 and DQ11 switch from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3 and DQ11. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 (Toggle Bits I) to ensure that the device has accepted the command sequence, and then read DQ3 and DQ11. If DQ3 and DQ11 are "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 and DQ11 are "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 and DQ11 prior to and following each subsequent sector erase command. If DQ3 and DQ11 are high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 and DQ11 relative to the other status bits.
DQ5 and DQ13: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 and DQ13 produce a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 and/or DQ13 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 and/or DQ13 produces a "1." In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
36
Am29LV6402M
January 23, 2006
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 and DQ9 produce a "1". The system must issue the
Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Programming section for more details.
Table 12.
Write Operation Status
DQ5/ DA13 (Note 1) 0 0 DQ3/ DQ11 N/A 1 DQ2/DQ10 (Note 2) No toggle Toggle DQ1/ DQ9 0 N/A
Status Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Program-Suspended Program Program- Sector Suspend Suspend Non-Program Mode Read Suspended Sector Erase-Suspended 1 EraseSector Suspend Erase Non-Erase Read Suspend Suspended Sector Mode Erase-Suspend-Program DQ7/DQ15# (Embedded Program) DQ7/DQ15# Write-to- Busy (Note 3) Buffer Abort (Note 4) DQ7/DQ15#
DQ7/DQ15 (Note 2) DQ6/DQ14 DQ7/DA15# Toggle 0 Toggle
RY/BY# 0 0 1 1
Invalid (not allowed) Data No toggle 0 Data Toggle Toggle Toggle 0 0 0 N/A N/A N/A N/A N/A N/A N/A 0 1 N/A Toggle N/A
1 1 0 0 0
Notes: 1. DQ5 and DQ13 switch to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 and DQ13 for more information. 2. DQ7 and DQ15 and DQ2 and DQ10 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 and DQ9 switch to `1' when the device has aborted the write-to-buffer operation.
January 23, 2006
Am29LV6402M
37
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE#, WP#/ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. Dur ing voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 10. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 11. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, WP#/ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns
Figure 10. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 11. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0-3.6 V VIO (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 1.65-3.6 V
4. Operating ranges define those limits between which the functionality of the device is guaranteed. 5. See ordering information for valid VCC/VIO combinations. The I/Os will not operate at 3 V when VIO = 1.8 V
38
Am29LV6402M
January 23, 2006
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 Parameter Description (Notes) Input Load Current (1) A9, ACC Input Load Current Output Leakage Current VCC Active Read Current (2, 3) VCC Initial Page Read Current (2, 3) Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max 1 MHz CE# = VIL, OE# = VIH, 5 MHz 1 MHz CE# = VIL, OE# = VIH 10 MHz 10 MHz VCC Intra-Page Read Current (2, 3) VCC Active Write Current (3, 4) VCC Standby Current (3) VCC Reset Current (3) Automatic Sleep Mode (3, 5) Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage VCC = 2.7 -3.6 V VCC = 2.7 -3.6 V IOL = 4.0 mA, VCC = VCC min IOL = 100 A, VCC = VCC min Output High Voltage Low VCC Lock-Out Voltage (6) IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 2.4 VCC - 0.1 2.3 2.5 V CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE#, RESET# = VCC 0.3 V, WP# = VIH RESET# = VSS 0.3 V, WP# = VIH VIH = VCC 0.3 V; VIL = VSS 0.3 V, WP# = VIH -0.5 1.9 11.5 11.5 33 MHz 6 26 8 80 6 12 100 2 2 2 Min Typ Max 2.0 70 2.0 68 mA 86 100 160 40 80 120 10 10 10 0.8 VIO + 0.3 12.5 12.5 0.4 0.1 mA mA mA mA mA A A A V V V V V V V Unit A A A
ICC2
ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VHH VID VOL
VOH VLKO
Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is 10.0 A. 2. The ICC current listed is typically less than 4 mA/MHz, with OE# at VIH. 3. Maximum ICC specifications are tested with VCC = VCCmax.
4. 5.
6.
ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
Not 100% tested.
January 23, 2006
Am29LV6402M
39
TEST CONDITIONS
Table 13.
3.3 V Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels
Test Specifications
All Speeds 1 TTL gate 30 5 0.0-3.0 1.5 0.5 VIO pF ns V V V Unit
Device Under Test
2.7 k
Note: Diodes are IN3064 or equivalent.
Figure 12.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
3.0 V 0.0 V
Input
1.5 V
Measurement Level
0.5 VIO V
Output
Figure 13. Input Waveforms and Measurement Levels
40
Am29LV6402M
January 23, 2006
AC CHARACTERISTICS Read-Only Operations
Parameter JEDEC Std. Description tAVAV tAVQV tELQV tRC Read Cycle Time (Note 1) Test Setup Min CE#, OE# = VIL Max OE# = VIL Max Max Max Max Max Min Min Min Speed Options 100R 100 100 100 30 30 25 25 0 0 10 110R 110 110 110 30 30 Unit ns ns ns ns ns ns ns ns ns ns
tACC Address to Output Delay tCE Chip Enable to Output Delay
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Read Output Enable Hold Toggle and Time (Note 1) Data# Polling
tOEH
Notes: 1. Not 100% tested. 2. See Figure 12 and Table 13 for test specifications.
3. AC Specifications are tested with VIO=VCC. Please contact the factory for information on using the device with VIO VCC.
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 14.
Read Operation Timings
January 23, 2006
Am29LV6402M
41
AC CHARACTERISTICS
A21-A2 Same Page
A1-A0*
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Qa
Qb
Qc
Qd
* Figure shows doubleword mode. Addresses are A1-A-1 for word mode.
Figure 15.
Page Read Timings
42
Am29LV6402M
January 23, 2006
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std. tReady tReady tRP tRH tRPD 1. Not 100% tested 2. AC Specifications are tested with VIO=VCC. Please contact the factory for information on using the device with VIO VCC. Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode Max Max Min Min Min All Speed Options 20 500 500 50 20 Unit s ns ns ns s
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 16.
Reset Timings
January 23, 2006
Am29LV6402M
43
AC CHARACTERISTICS Erase and Program Operations
Speed Options Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Single Doubleword/Word Program Operation (Note 2) Accelerated Single Doubleword/Word Programming Operation (Note 2) tWHWH2 tWHWH2 tVHH tVCS Sector Erase Operation (Note 2) VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) Per Word Per Doubleword Per Word Per Doubleword Word Doubleword Word Doubleword Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Min Min 100R 100 0 15 45 0 45 0 20 0 0 0 35 30 352 11 22 8.8 17.6 100 100 90 90 0.5 250 50 110R 110 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s s s sec ns s
tWHWH1
tWHWH1
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 doublewords/1-32 words programmed. 4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. AC Specifications are tested with VIO=VCC. Please contact the factory for information on using the device with VIO VCC.
44
Am29LV6402M
January 23, 2006
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 18.
Accelerated Program Timing Diagram
January 23, 2006
Am29LV6402M
45
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 2. These waveforms are for the doubleword mode.
Figure 19.
Chip/Sector Erase Operation Timings
46
Am29LV6402M
January 23, 2006
AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
January 23, 2006
Am29LV6402M
47
AC CHARACTERISTICS
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6 and DQ14. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 21.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE# DQ6, DQ14
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ2, DQ10 Note: DQ2 and DQ10 toggle only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ1- and DQ6 and DQ14.
Figure 22. DQ2 vs. DQ6
48
Am29LV6402M
January 23, 2006
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP 1. Not 100% tested. 2. AC Specifications are tested with VIO=VCC. Please contact the factory for information on using the device with VIO VCC. Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID VSS, VIL, or VIH
WE# tRSP RY/BY# tRRB
Figure 23.
Temporary Sector Group Unprotect Timing Diagram
January 23, 2006
Am29LV6402M
49
AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect or Unprotect
Valid* Verify 40h
Sector Group Protect: 150 s, Sector Group Unprotect: 15 ms
Valid*
Data
60h
60h
Status
1 s CE#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24.
Sector Group Protect and Unprotect Timing Diagram
50
Am29LV6402M
January 23, 2006
AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Speed Options Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Single Doubleword/Word Program Operation (Note 2) Accelerated Single Doubleword/Word Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Per Word Per Doubleword Per Word Per Doubleword Word Doubleword Word Doubleword Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ 100R 100 0 45 45 0 0 0 0 45 30 352 11 22 8.8 17.6 100 100 90 90 0.5 110R 110 Unit ns ns ns ns ns ns ns ns ns ns s s s s s s s s s sec
tWHWH1
tWHWH1
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 doublewords/1-32 words programmed. 4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. AC Specifications are tested with VIO=VCC. Please contact the factory for information on using the device with VIO VCC.
January 23, 2006
Am29LV6402M
51
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# and DQ15# are the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 25.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA
52
Am29LV6402M
January 23, 2006
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Single Doubleword/Word Program Time (Note 3) Accelerated Single Doubleword/ Word Program Time Word Doubleword Word Doubleword Typ (Note 1) Max (Note 2) 0.5 32 100 100 90 90 352 Per Word Per Doubleword 11 22 282 8.8 17.6 92 15 128 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Unit sec sec s s s s s s s s s s sec Excludes system level overhead (Note 6) Comments Excludes 00h programming prior to erasure (Note 5)
Total Write Buffer Program Time (Note 4) Effective Write Buffer Program Time (Note 3)
Total Accelerated Write Buffer Program Time (Note 4) Effective Write Buffer Accelerated Program Time (Note 3) Chip Program Time Per Word Per Doubleword
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 10,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 4. For 1-16 doublewords or 1-32 words programmed in a single write buffer programming operation. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 10 and 11 for further information on command definitions.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 BGA BGA BGA Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
January 23, 2006
Am29LV6402M
53
PHYSICAL DIMENSIONS LSB080--80-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11 mm Package
0.20 C (2X)
8 7 6
D
A
D1 eD
SE
7
E eE
5 4 3 2 1
E1
INDEX MARK PIN A1 CORNER 10
K
J
H
G
F
E
D
C
B
A
B
7
TOP VIEW
0.20 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.25 C
A A2 A1
6
SIDE VIEW b
C
0.20 C
80X
0.25 M C A B 0.10 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.50 LSB 080 N/A 13.00 mm x 11.00 mm PACKAGE MIN --0.40 1.00 NOM ------13.00 BSC. 11.00 BSC. 9.00 BSC. 7.00 BSC. 10 8 80 0.60 1.00 BSC. 1.00 BSC 0.50 BSC. 0.70 MAX 1.60 --1.11 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3265 \ 16-038.15a
54
Am29LV6402M
January 23, 2006
REVISION SUMMARY Revision A (January 20, 2003)
Initial release. Changed values for the following parameters: Write Buffer Program Operation, Effective Write Buffer Program Operation, Accelerated Effective Write Buffer Program Operation, Sector Erase Operation, Single Doubleword/Word Program Operation, Accelerated Single Doubleword/Word Program Operation (the phrase "Single Doubleword/Word" was added to the last two parameter titles). Erase and Programming Performance Changed typical sector erase time. Changed typical chip erase time and added maximum erase time. Replaced TBDs for all typical specifications with actual values. Added phrase "Single Doubleword/Word" to Program Time and Accelerated Program Time parameters titles. Added Total Write Buffer Program Time and Total Accelerated Write Buffer Program Time parameters to table. Changed device endurance in Note 1 to 10,000 cycles. Changed write buffer operation size in Note 3. Note 4 now refers to write buffer programming instead of chip programming. Deleted Note 7.
Revision B (September 17, 2003)
Global Changed data sheet status from Advance Information to Preliminary. Distinctive Characteristics Changed description of device erase cycle endurance. Changed typical sector erase time, typical write buffer programming time, and typical active read current specification. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. Erase Suspend/Erase Resume Commands Deleted reference to erase-suspended sector address requirement for commands. Tables 10 and 11, Command Definitions Corrected addresses for Erase Suspend and Erase Resume to "XXX" (don't care). DC Characteristics Changed typical and maximum values for ICC1, ICC2, and ICC3. Values for different frequencies were added to ICC2 and ICC3. AC Characteristics Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table.
Revision B+1 (January 23, 2006)
This product has been retired and is not available for designs. For new and current designs, S29GL128N supersedesS29LV6402M and is the factory-recomm e n d e d m i g r a t i o n p a t h . P l e a s e r e fe r t o t h e S29GL128N Data Sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Updated migration statement on cover page and first page of data sheet. Updated trademarks.
Trademarks Copyright (c) 2005-2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
January 23, 2006
Am29LV6402M
55

▲Up To Search▲

Price & Availability of AM29LV6402MH110RPHI

	To Download AM29LV6402MH110RPHI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .